1. Field of the Invention
The present invention generally relates to a PLL (Phase-Locked Loop) circuit and, in particular, to a PLL synthesizer which selectively generates a plurality of frequency signals.
2. Description of the Related Art
For a PLL synthesizer employed in a mobile communication terminal, it is required to selectively generate a plurality of frequencies with high speed switching and high stability. To meet such requirements, there have been proposed several circuits.
A PLL synthesizer disclosed in Japanese Patent Unexamined Publication No. 5-335944 is provided with a plurality of low-pass filters one of which is selected by a first selector and a second selector to provide a different loop gain. A selected low-pass filter receives a tuning voltage from a phase comparator through the first selector, holds the tuning voltage, and then outputs the held tuning voltage to a voltage controlled oscillator (VCO) through the second selector.
Another PLL synthesizer disclosed in Japanese Patent Unexamined Publication No. 4-235416 is provided with a plurality of low-pass filters, first and second selectors and an initial setting circuit. The first and second selectors select one of the low-pass filters providing different loop gains when switching of frequencies. Just after the switching occurs, the initial setting circuit adjusts the phase of a variable-divided output of the VCO for synchronization with that of a reference signal generated by a reference oscillator. This results in high speed frequency switching.